View MTV012A_1542036.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

myson technology MTV012A 8051 embedded crt monitor controller mask version this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. mtv012 a revisi on 1. 1 12 /23/1998 1/ 14 features 8051 core. 256 bytes internal ram. 8k bytes program mask rom. 14 channels 10v open drain pwm dac, 10 dedicated channels and 4 channels shared with i/o pin. 20 bi-direction i/o pin, 12 dedicated pin, 4 shared with dac, 4 shared with ddc/iic interface. 3 output pins shared with h/v sync output and self test output pins. sync processor for composite sync separation, polarity and frequency check, and polarity adjustment. built-in monitor self test pattern generator. built-in low power reset circuit. iic interface for ddc1/ddc2b and eeprom, only one eeprom needed to store ddc1/ddc2b and display mode information. watch dog timer with programmable interval. 40 pin pdip package. general description the MTV012A micro controller is an 8051 cpu core-embedded device specially tailored to crt monitor applications. it includes an 8051 cpu core, 256-byte sram, 14 built-in pwm dacs, ddc1/ddc2b interface, 24cxx series eeprom interface and an 8k-byte internal program rom. block diagram xfr 8051 core p1.0-7 x1 x2 p2.0-3 p3.0-p3.2 p3.4 p0.0-7 rd wr int1 rst p2.4-7 rd wr p0.0-7 watch-dog timer rst h/ vsync control hsync vsync hblank vblank stout 14 channel pwm dac ddc 1/2 b & fifo interface hscl hsda iic interface isda iscl da10-13 da0-9
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 2 / 14 1.0 pin connection 2.0 pin description name type pin# description p1.0 i/o 1 general purpose i/o. p1.1 i/o 2 general purpose i/o. p1.2 i/o 3 general purpose i/o. p1.3 i/o 4 general purpose i/o. p1.4 i/o 5 general purpose i/o. p1.5 i/o 6 general purpose i/o. p1.6 i/o 7 general purpose i/o. p1.7 i/o 8 general purpose i/o. rst i 9 active high reset. hscl/p3.0/rxd i/o 10 iic clock / general purpose i/o / rxd. hsda/p3.1/txd i/o 11 iic data / general purpose i/o / txd. isda/p3.2/int0 i/o 12 iic data / general purpose i/o / int0. hsync i 13 horizontal sync or composite sync. iscl/p3.4/t0 i/o 14 iic clock / general purpose i/o / t0. vsync i 15 vertical sync. hblank/p4.1 o 16 horizontal blank / general purpose output. vblank/p4.0 o 17 vertical blank / general purpose output. x2 o 18 oscillator output. x1 i 19 oscillator input. vss - 20 negative power supply. p2.0 /int0 i/o 21 general purpose i/o / int0. MTV012A p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 rst hscl/p3.0/rxd hsda/p3.1/txd isda/p3.2/int0 hsync iscl/p3.4/t0 vsync hblank/p4.1 vblank/p4.0 x2 x1 vss vdd da0 da1 da2 da3 da4 da5 da6 da7 da8 da9 stout/p4.2 da10/p2.7 da11/p2.6 da12/p2.5 da13/p2.4 p2.3 p2.2 p2.1 p2.0/int0
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 3 / 14 p2.1 i/o 22 general purpose i/o. p2.2 i/o 23 general purpose i/o. p2.3 i/o 24 general purpose i/o. da13/p2.4 i/o 25 pwm dac output / general purpose i/o (open-drain). da12/p2.5 i/o 26 pwm dac output / general purpose i/o (open-drain). da11/p2.6 i/o 27 pwm dac output / general purpose i/o (open-drain). da10/p2.7 i/o 28 pwm dac output / general purpose i/o (open-drain). stout/p4.2 o 29 self-test video output / general purpose output. da9 o 30 pwm dac output (open-drain). da8 o 31 pwm dac output (open-drain). da7 o 32 pwm dac output (open-drain). da6 o 33 pwm dac output (open-drain). da5 o 34 pwm dac output (open-drain). da4 o 35 pwm dac output (open-drain). da3 o 36 pwm dac output (open-drain). da2 o 37 pwm dac output (open-drain). da1 o 38 pwm dac output (open-drain). da0 o 39 pwm dac output (open-drain). vdd - 40 positive power supply. 3.0 functional description 1. 8051 cpu core MTV012A includes all the 8051 functions with the following exceptions: 1.1 psen, ale, rd and wr pins are disabled. the external ram access is restricted to xfrs within MTV012A. 1.2 port0, port3.3 and ports3.5 ~ 3.7 are not general purpose i/o ports. they are dedicated to monitoring control/dac pins. 1.3 int1 and t1 input pins are not provided. 1.4 ports2.4 ~ 2.7 are shared with dac pins; ports3.0 ~ 3.2 and port3.4 are shared with monitor control pins. in addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard 8051. the txd/ rxd (p3.0/p3.1) pins are shared with the ddc interface. int0/t0 pins are shared with the iic interface. an extra option can be used to switch the int0 source from p3.2 to p2.0. this feature maintains an external interrupt source when the iic interface is enabled. note: all registers listed in this document reside in the external ram area (xfr). for the internal ram memory map, please refer to the 8051 spec. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 padmod 30h (w) sint0 x ddce iice da13e da12e da11e da10e sint0 = 1 ? int0 source is pin #21. = 0 ? int0 source is pin #12. ddce = 1 ? pin #10 is hscl; pin #11 is hsda. = 0 ? pin #10 is p3.0/rxd; pin #11 is p3.1/txd. iice = 1 ? pin #12 is isda; pin #14 is iscl. = 0 ? pin #12 is p3.2/(int0*); pin #14 is p3.4/t0. da13e = 1 ? pin #25 is da13. = 0 ? pin #25 is p2.4. da12e = 1 ? pin #26 is da12. = 0 ? pin #26 is p2.5.
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 4 / 14 da11e = 1 ? pin #27 is da11. = 0 ? pin #27 is p2.6. da10e = 1 ? pin #28 is da10. = 0 ? pin #28 is p2.7. * sint0 should be 0 in this case. 2. external special function registers (xfr) the xfr is a group of registers allocated in the 8051 external ram area. most of the registers are used for monitor control or pwm dac. the program can initialize ri value and use "movx" instruction to access these registers. 3. pwm dac each d/a converter's output pulse width is controlled by an 8-bit register in the xfr. the frequency of these outputs is ( xtal frequency)/253 or ( xtal frequency)/256, selected by div253. if div253=1, writing fdh/feh/ffh to the dac register generates a stable high output. if div253=0, the output will pulse low at least once even if the dac register's content is ffh. writing 00h to the dac register generates stable low output. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 da0 20h (r/w) da0 b7 da0 b6 da0 b5 da0 b4 da0 b3 da0 b2 da0 b1 da0 b0 da1 21h (r/w) da1 b7 da1 b6 da1 b5 da1 b4 da1 b3 da1 b2 da1 b1 da1 b0 da2 22h (r/w) da2 b7 da2 b6 da2 b5 da2 b4 da2 b3 da2 b2 da2 b1 da2 b0 da3 23h (r/w) da3 b7 da3 b6 da3 b5 da3 b4 da3 b3 da3 b2 da3 b1 da3 b0 da4 24h (r/w) da4 b7 da4 b6 da4 b5 da4 b4 da4 b3 da4 b2 da4 b1 da4 b0 da5 25h (r/w) da5 b7 da5 b6 da5 b5 da5 b4 da5 b3 da5 b2 da5 b1 da5 b0 da6 26h (r/w) da6 b7 da6 b6 da6 b5 da6 b4 da6 b3 da6 b2 da6 b1 da6 b0 da7 27h (r/w) da7 b7 da7 b6 da7 b5 da7 b4 da7 b3 da7 b2 da7 b1 da7 b0 da8 28h (r/w) da8 b7 da8 b6 da8 b5 da8 b4 da8 b3 da8 b2 da8 b1 da8 b0 da9 29h (r/w) da9 b7 da9 b6 da9 b5 da9 b4 da9 b3 da9 b2 da9 b1 da9 b0 da10 2ah (r/w) da10 b7 da10 b6 da10 b5 da10 b4 da10 b3 da10 b2 da10 b1 da10 b0 da11 2bh (r/w) da11 b7 da11 b6 da11 b5 da11 b4 da11 b3 da11 b2 da11 b1 da11 b0 da12 2ch (r/w) da12 b7 da12 b6 da12 b5 da12 b4 da12 b3 da12 b2 da12 b1 da12 b0 da13 2dh (r/w) da13 b7 da13 b6 da13 b5 da13 b4 da13 b3 da13 b2 da13 b1 da13 b0 wdt 80h wen wclr clrddc div253 x wdt2 wdt1 wdt0 da0 (r/w ) : the output pulse width control for da0. da1 (r/w ) : the output pulse width control for da1. da2 (r/w ) : the output pulse width control for da2. da3 (r/w ) : the output pulse width control for da3. da4 (r/w ) : the output pulse width control for da4. da5 (r/w ) : the output pulse width control for da5. da6 (r/w ) : the output pulse width control for da6. da7 (r/w ) : the output pulse wi dth control for da7. da8 (r/w ) : the output pulse width control for da8. da9 (r/w ) : the output pulse width control for da9. da10 (r/w ) : the output pulse width control for da10. da11 (r/w ) : the output pulse width control for da11. da12 (r/w ) : the output pulse width control for da12. da13 (r/w ) : the output pulse width control for da13. wdt (w ) : watchdog timer & special control bit. div253 = 1 ? the pwm dac output frequency is ( xtal frequency)/253. = 0 ? the pwm dac output frequency is ( xtal frequency)/256. *1. all d/a converters are centered with value 80h after power-on.
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 5 / 14 4. h/v sync processing the h/v sync processing block performs the functions of composite signal separation, sync input presence check, frequency counting, and polarity detection and control, as well as protection of vblank output while vsync speeds up to a high ddc communication clock rate. the present and frequency function block treat any pulse shorter than 1 osc period as noise. 4.1 composite sync separate MTV012A continuously monitors the input hsync. if the vertical sync pulse can be extracted from the input, a cvpre flag is set and the user can select the extracted "cvsync" for the source of polarity check, frequency count and vblank. the cvsync will have a 10-16 us delay compared to the original signal. the delay depends on the osc frequency and composite mix method. 4.2 h/v frequency counter MTV012A can discriminate between hsync/vsync frequency and saves the information in xfrs. the 15-bit h counter counts the time of the 64xhsync period, but only 11 upper bits are loaded into the hcnth/hcntl latch. the 11-bit output value will be (2/hfreq) / (1/oscfreq), updated once per vsync/cvsync period when vsync/cvsync is present, or continuously updated when vsync/cvsync is not present. the 14-bit v counter counts the time between 2 vsync pulses, but only 9 upper bits are loaded into the vcnth/vcntl latch. the 9-bit output value will be (1/vfreq) / (512/oscfreq ), updated every vsync/cvsync period. an extra overflow bit indicates the condition of h/v counter overflow. the vfchg/ hfchg interrupt is active when vcnt/hcnt value changes or overflows. tables 4.2.1 and 4.2.2 show the hcnt/vcnt value under the 8mhz osc operations. 4.2.1 h- freq table output value (11 bits) h- freq( khz) 8mhz osc (hex / dec) 12mhz osc (hex / dec) 1 30 215h / 533 320h / 800 2 31.5 1fbh / 507 2f9h / 761 3 33.5 1ddh /477 2cch / 716 4 35.5 1c2h / 450 2a4h / 676 5 36.8 1b2h / 434 28ch / 652 6 38 1a5h / 421 277h / 631 7 40 190h / 400 258h / 600 8 48 14dh / 333 1f4h / 500 9 50 140h / 320 1e0h / 480 10 57 118h / 280 1a5h / 421 11 60 10ah / 266 190h / 400 12 64 0fah / 250 177h / 375 13 100 0a0h / 160 0f0h / 240 *1. the h- freq output (hf10 - hf0) is valid. *2. the tolerance deviation is + 1 lsb. 4.2.2 v- freq table output value (9 bits) v- freq(hz) 8mhz osc (hex / dec) 12mhz osc (hex / dec) 1 56.25 115h / 277 1a0h / 416 2 59.94 104h / 260 187h / 391 3 60 104h / 260 186h / 390 4 60.32 103h / 259 184h / 388
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 6 / 14 5 60.53 102h / 258 183h / 387 6 66.67 0eah / 234 15fh / 351 7 70.069 0deh / 222 14eh / 334 8 70.08 0deh / 222 14eh / 334 9 72 0d9h /217 145h / 325 10 72.378 0d7h / 215 143h / 323 11 72.7 0d6h / 214 142h / 322 12 87 0b3h / 179 10dh / 269 *1. the v- freq output (vf8 - vf0) is valid. *2. the tolerance deviation is + 1 lsb. 4.3 h/v present check the h present function checks the input hsync pulse; the hpre flag is set when hsync is over 10khz or cleared when hsync is under 10hz. the v present function checks the input vsync pulse; the vpre flag is set when vsync is over 40hz or cleared when vsync is under 10hz. the control bit "prefs" selects the time base for these functions. the hprchg interrupt is set when the hpre value changes. the vprchg interrupt is set when the vpre/ cvpre values change. however, the cvpre flag interrupt may be disabled when s/w disables the composite function. 4.4 h/v polarity detection the polarity functions detect the input hsync/vsync high and low pulse duty cycle. if the high pulse duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive polarity is asserted. the hplchg interrupt is set when the hpol value changes. the vplchg interrupt is set when the vpol value changes. 4.5 output hblank/vblank control and polarity adjustment hblank is the mux output of hsync and the self-test horizontal pattern. the vblank is the mux output of vsync, cvsync and the self-test vertical pattern. the mux selection and output polarity are s/w controllable. the vblank output is cut off when vsync frequency is over 200hz or 133hz depends on 8mhz/12mhz osc selection. hblank/vblank shares the output pin with p4.1/ p4.0. 4.6 self-test pattern generator this generator can generate 4 display patterns for testing purposes: positive cross-hatch, negative cross-hatch, full white and full black (shown in the following figure). it was originally designed to support monitor manufacturers to do a burn-in test, or offer the end-user a reference to check the monitor. the generator's output stout shares the output pin with p4.2. display region self-test patterns (1)
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 7 / 14 self-test patterns (2) 4.7 h/v sync processor register present check digital filter present check vpre frequency count vfreq polarity check vpol high frequency mask vself cvsync polarity check & sync seperator cvpre hpol hself digital filter present check & frequency count hpre hfreq hbpl vbpl vblank hblank vsync hsync h/v sync processor block diagram reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pstus 40h (r) cvpre x hpol vpol hpre vpre hoff voff hcnth 41h (r) hovf x x x x hf10 hf9 hf8 hcntl 42h (r) hf7 hf6 hf5 hf4 hf3 hf2 hf1 hf0 vcnth 43h (r) vovf x x x x x x vf8 vcntl 44h (r) vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 pctr0 40h (w) c1 c0 hvsel stosel prefs halfv hbpl vbpl pctr2 42h (w) x x x selft st bsh rt1 rt0 stf p4out 44h (w) x x x x x p42 p41 p40 intflg 50h (r/w) hprchg vprchg hplchg vplchg hfchg vfchg fifoi mi inten 60h (w) ehpr evpr ehpl evpl ehf evf efifo emi pstus (r): the status of polarity, present and static level for hsync and vsync. cvpre = 1 ? the extracted cvsync is present. = 0 ? the extracted cvsync is not present. h pol = 1 ? hsync input is positive polarity.
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 8 / 14 = 0 ? hsync input is negative polarity. v pol = 1 ? vsync (cvsync) is positive polarity. = 0 ? vsync (cvsync) is negative polarity. h pre = 1 ? hsync input is present. = 0 ? hsync input is not present. v pre = 1 ? vsync input is present. = 0 ? vsync input is not present. h off* = 1 ? hsync input's off-level is high. = 0 ? hsync input's off-level is low. v off* = 1 ? vsync input's off-level is high. = 0 ? vsync input's off-level is low. *h off and v off are valid when h pre=0 or v pre=0. hcnth (r ) : h- freq counter's high bits. hovf = 1 ? h- freq counter overflows; this bit is cleared by h/w when condition removed. hf10 - hf8 : 3 high bits of h- freq counter. hcntl (r ) : h- freq counter's low bits. vcnth (r ) : v- freq counter's high bits. vovf = 1 ? v- freq counter overflows; this bit is cleared by h/w when condition removed. vf8 : high bit of v- freq counter. vcntl (r ) : v- freq counter's low bits. pctr0 (w ) : sync processor control register 0. c1, c0 = 1,1 ? selects cvsync as the polarity, freq and vblank source. = 1,0 ? selects vsync as the polarity, freq and vblank source. = 0,0 ? disables composite function (mtv012 compatible mode). = 0,1 ? h/w auto switch to cvsync when cvpre=1 and vspre=0. hvsel = 1 ? pin #16 is p41, pin #17 is p40. = 0 ? pin #16 is hblank, pin #17 is vblank. stosel = 1 ? pin #29 is p42. = 0 ? pin #29 is stout. prefs = 0 ? selects 8mhz osc as h/v present check and self-test pattern time base. = 1 ? selects 12mhz osc as h/v present check and self-test pattern time base. halfv = 1 ? vblank is half frequency output of vsync. hb pl = 1 ? negative polarity hblank output. = 0 ? positive polarity hblank output. vb pl = 1 ? negative polarity vblank output. = 0 ? positive polarity vblank output. pctr2 (w ) : self-test pattern generator control. s elft = 1 ? enables generator. = 0 ? disables generator. st bsh = 1 ? 63.5khz (horizontal) output selected. = 0 ? 31.75khz (horizontal) output selected. rt1 ,rt0 = 0,0 ? positive cross-hatch pattern output. = 0,1 ? negative cross-hatch pattern output. = 1,0 ? full white pattern output. = 1,1 ? full black pattern output.
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 9 / 14 stf = 1 ? enables stout output. = 0 ? disables stout output. p4out (w ) : port 4 data output value. intflg (w ) : interrupt flag. an interrupt event will set its individual flag, and, if the corresponding interrupt enable bit is set, the 8051 core's int1 source will be driven by a zero level. software must clear this register while serving the interrupt routine. hprchg= 1 ? no action. = 0 ? clears hsync presence change flag. vprchg= 1 ? no action. = 0 ? clears vsync presence change flag. hplchg = 1 ? no action. = 0 ? clears hsync polarity change flag. vplchg = 1 ? no action. = 0 ? clears vsync polarity change flag. hfchg = 1 ? no action. = 0 ? clears hsync frequency change flag. vfchg = 1 ? no action. = 0 ? clears vsync frequency change flag. intflg (r ) : interrupt flag. hprchg= 1 ? indicates an hsync presence change. vprchg= 1 ? indicates a vsync presence change. hplchg = 1 ? indicates an hsync polarity change. vplchg = 1 ? indicates a vsync polarity change. hfchg = 1 ? indicates an hsync frequency change or counter overflow. vfchg = 1 ? indicates a vsync frequency change or counter overflow. inten (w ) : interrupt enabler. ehpr = 1 ? enables hsync presence change interrupt. evpr = 1 ? enables vsync presence change interrupt. ehpl = 1 ? enables hsync polarity change interrupt. evpl = 1 ? enables vsync polarity change interrupt. ehf = 1 ? enables hsync frequency change / counter overflow interrupt. evf = 1 ? enables vsync frequency change / counter overflow interrupt. 5. ddc & iic interface 5.1 ddc1 mode MTV012A enters ddc1 mode after reset. in this mode, vsync is used as a data clock when the hscl pin remains at high. the data stream taken from an 8-bit fifo in MTV012A is sent in a 9-bit packet that includes a null bit (=1) as packet separator. the software program should take care of the fifo depth. the fifo generates a fifoi interrupt when there are fewer than n (n = 1, 2, 3 or 4 controlled by ls1, ls0) bytes to be output to the hsda line. on the other hand, the fifo sets the fifoh flag when there are more than 7 bytes queuing for output. the fifoi interrupt can be enabled or disabled by s/w. a simple way to control fifo is to set {ls1 ,ls0}={1,0} and enable fifoi, then load fifo 4 bytes every time a fifoi interrupt occurs. a special control bit "ldfifo" can reduce s/w effort when edid data is saved in eeprom. if ldfifo=1, fifo will be automatically loaded when s/w reads mbuf xfr. 5.2 ddc2b mode MTV012A switches to ddc2b mode when it detects a high to low transition on the hscl pin. once MTV012A enters ddc2b mode, the host can access the eeprom using iic bus protocol as if the hsda and hscl are directly bypassed to isda and iscl pins. MTV012A will return to ddc1 mode if hscl is kept high for a 128-vsync clock period. however, it will permanently remain in ddc2b mode if a valid iic access has been detected on the hscl/hsda bus. the ddc2 flag reflects the current ddc
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 10 / 14 status; s/w may clear it by setting clrddc. the control bits m128/m256 are used to block the eeprom write operation from the host if the address is over 128/256. 5.3 master mode iic function block the master mode iic block is connected to the isda and iscl pins. the software program can access the external eeprom through this interface. since the edid/vdif data and the display information share the common eeprom, precaution must be taken to avoid bus conflict. in ddc1 mode, the iic interface is controlled by MTV012A only. in ddc2b mode, the host may access the eeprom directly. software can test the hscl condition by reading the busy flag, which is set in case of hscl=0. a summary of master iic access is illustrated as follows: 5.3.1. to write eeprom 1. write to mbuf the eeprom slave address (bit 0 = 0). 2. set s bit to start. 3. after MTV012A transmits this byte, a mi interrupt will be triggered. 4. the program can write mbuf to transfer the next byte, or set the p bit to stop. * please see the attachments about "master iic transmission timing". 5.3.2. to read eeprom 1. write to mbuf the slave address (bit 0 = 1). 2. set the s bit to start. 3. after MTV012A transmits this byte, a mi interrupt will be triggered. 4. set or reset the ack flag according to the iic protocol. 5. read out to mbuf the useless byte in order to continue the data transfer. 6. after MTV012A receives a new byte, the mi interrupt is triggered again. 7. reading mbuf also triggers the next receiving operation, but the p bit needs to be set before reading can terminate the operation. * please see the attachments about the "master iic timing receiving". 5.4 slave mode iic function block the slave mode iic block can be connected to hsda/hscl pins or isda/iscl pins, and selected by the slvsel control bit. this block is receiving mode only. s/w may set the slvadr register to determine the address range to which this block should respond. the block first detects an iic slave address match condition , then issues a slvmi interrupt. the data received from sda is shifted onto the shift register and moved to the slvbuf latch. the first byte loaded is the word address (the slave address is dropped). this block also generates a slvbi each time the slvbuf is loaded. if s/w can't read out the slvbuf in time, the next byte will not be written to slvbuf and the slave block returns nack to the master. this feature guarantees the data integrity of communication. a wadr flag can tell s/w if the data in slvbuf is a word address. * please see the attachments about "slave iic block timing". 6. low power reset (lvr) & watchdog timer when the voltage level of the power supply is below 4.0v for a specific time, the lvr will generate a chip reset signal. after the power supply is above 4.0v, lvr maintains the reset state for a 144 xtal cycle to guarantee that the chip exit reset condition has a stable xtal oscillation. the specific time of power supply in the low level is 3us and is adjustable by an external capacitor connected to the rst pin. the watchdog timer automatically generates a device reset when it overflows. the interval of overflow is 0.25 sec x n, in which n is a number from 1 to 8, and can be programmed via register wdt(2:0). the timer function is disabled after power-on reset; the user can activate this function by setting wen, and clear the timer by setting wclr. reg name addr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 mstus 00h (r) x sclerr ddc2 berr hfreq fifoh fifol busy mbuf 10h (r/w) mbuf7 mbuf6 mbuf5 mbuf4 mbuf3 mbuf2 mbuf1 mbuf0 intflg 50h (r/w) hprchg vprchg hplchg vplchg hfchg vfchg fifoi mi
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 11 / 14 mctr 00h (w) ls1 ls0 ldfifo m256 m128 ack p s inten 60h (w) ehpr evpr ehpl evpl ehf evf efifo emi fifo 70h (w) fifo7 fifo6 fifo5 fifo4 fifo3 fifo2 fifo1 fifo0 wdt 80h (w) wen wclr clrddc div253 lvsel wdt2 wdt1 wdt0 slvctr 90h (w) enslv slvsel eslvbi eslvmi x x x x slvstus 91h (r) wadr slvs slvbi slvmi x x x x slvint 91h (w) x x x slvmi x x x x slvbuf 92h (r) slvbuf7 slvbuf6 slvbuf5 slvbuf4 slvbuf3 slvbuf2 slvbuf1 slvbuf0 slvadr 93h (w) slvadr7 slvadr6 slvadr5 slvadr4 slvadr3 slvadr2 slvadr1 x mctr (w ) : master iic interface control register. ls1, ls0 = 11 ? fifol is the status which has a fifo depth of < 5. = 10 ? fifol is the status which has a fifo depth of < 4. = 01 ? fifol is the status which has a fifo depth of < 3. = 00 ? fifol is the status which has a fifo depth of < 2. ldfifo = 1 ? fifo will be written while s/w reads mbuf. m256 = 1 ? disables host writing eeprom when address is over 256. m128 = 1 ? disables host writing eeprom when address is over 128. ack = 1 ? in receiving mode, there is no acknowledgment by MTV012A. = 0 ? in receiving mode, ack is returned by MTV012A. s, p = - ,0 ? start condition when master iic is not transferring. = x, - ? stop condition when master iic is not transferring. = 1,x ? will resume transfer after a read/write mbuf operation. = x ,0 ? forces hscl low and occupies the iic bus. * MTV012A uses a 100khz clock to sample the s/p bit; any pulse should sustain at least 20us. * a write/read mbuf operation can be recognized only after 10us of the mi flag's rising edge. mstus (r ) : master iic interface status register. sclerr = 1 ? the iscl pin is pulled-low by other devices during the transfer, and cleared when s=0. ddc2 = 1 ? ddc2b is active. = 0 ? MTV012A remains in ddc1 mode. berr = 1 ? iic bus error, no ack received from the slave, updated every time when slave sends ack on the isda pin. hfreq = 1 ? MTV012A detects a higher than 200hz clock on the vsync pin. fifoh = 1 ? fifo high indicated. fifol = 1 ? fifo low indicated. busy = 1 ? host drives the hscl pin to low. * while writing fifo, the fifoh/fifol flag will reflect the fifo condition after 30us. intflg (w ) : in terrupt flag. an interrupt event will set its individual flag and, if the corresponding interrupt enable bit is set, the 8051 int1 source will be driven by a zero level. software must clear this register while serving the interrupt routine. fifoi = 1 ? no action. = 0 ? clears fifoi flag. mi = 1 ? no action. = 0 ? clears master iic bus interrupt flag (mi). intflg (r ) : interrupt flag. fifoi = 1 ? indicates the fifo low condition; when efifo is set, MTV012A will be interrupted by int1. mi = 1 ? indicates when a byte is sent/received to/from the iic bus; when eepi is active, MTV012A will be interrupted by int1. inten (w ) : interrupt enabler. efifo = 1 ? enables fifo interrupt.
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 12 / 14 emi = 1 ? enables master iic bus interrupt. mbuf (w ) : master iic data shift register write; after start and before stop condition, this register will resume MTV012A's transmission to the iic bus. mbuf (r ) : master iic data shift register read; after start and before stop condition, this register will resume MTV012A's receiving from the iic bus. wdt (w ) : watchdog timer control register. wen = 1 ? enables the watchdog timer. wclr = 1 ? clears the watchdog timer. clrddc = 1 ? clears the ddc2 flag. lvsel = 1 ? low voltage reset will occur when vdd < 4.1v. = 0 ? low voltage reset will occur when vdd < 3.6v. wdt2: wdt0 = 0 ? overflow interval = 8 x 0.25 sec. = 1 ? overflow interval = 1 x 0.25 sec. = 2 ? overflow interval = 2 x 0.25 sec. = 3 ? overflow interval = 3 x 0.25 sec. = 4 ? overflow interval = 4 x 0.25 sec. = 5 ? overflow interval = 5 x 0.25 sec. = 6 ? overflow interval = 6 x 0.25 sec. = 7 ? overflow interval = 7 x 0.25 sec. fifo (w ) : writes fifo contents. slvctr (w ) : slave iic block control. enslv = 1 ? enables slave iic block. = 0 ? disables slave iic block. slvsel = 1 ? slave iic connects to isda/iscl. = 0 ? slave iic connects to hsda/hscl. eslvbi = 1 ? enables slave buffer interrupt. eslvmi = 1 ? enables slave address match interrupt. slvstus (r ) : slave iic block status. wadr = 1 ? the data in slvbuf is a word address. slvs = 1 ? the slave block has detected a start; will be cleared when stop is detected. slvbi = 1 ? slvbuf has been loaded with a new data byte; reset by s/w reading slvbuf. slvmi = 1 ? slave block has detected the slave address match condition; cleared by s/w writing 0 to slvmi. slvint (w ) : slave block interrupt. the slvbi/slvmi interrupt will set its flag, and, if the corresponding interrupt enable bit is set, the 8051 int1 source will be driven by a zero level. software must clear this register while serving the interrupt routine. slvmi = 1 ? no action. = 0 ? clears slvmi. slvbuf (r ) : slave iic data latch. slvadr (w ) : slave iic address to which the slave block should respond.
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 13 / 14 4.0 test mode condition in normal application, users should not allow mtv012 to enter its test/program mode, outlined as follows: test mode a: reset=1 & da9=0 & da8=1 & da7=1 & da6=0 test mode b: reset ? s falling edge & da9=1 & da8=0 & da7=1 & da6=0 5 .0 electrical parameters 5.1 absolute maximum ratings at: ta= 0 to 70 o c, vss=0v name symbol range unit maximum supply voltage vdd -0.3 to +6.0 v maximum input voltage vin -0.3 to vdd+0.3 v maximum output voltage vout -0.3 to vdd+0.3 v maximum operating temperature topg 0 to +70 o c maximum storage temperature tstg -25 to +125 o c 5 .2 allowable operating conditions at: ta= 0 to 70 o c, vss=0v name symbol min. max. unit supply voltage vdd 4.0 6.0 v input "h" voltage vih1 0.7 x vdd vdd +0.3 v input "l" voltage vil1 -0.3 0.15 x vdd v operating freq. fopg - 15 mhz 5 .3 dc characteristics at: ta=0 to 70 o c, vdd=4.0v ~ 6.0v, vss=0v name symbol condition min. typ. max. unit output "h" voltage; except open- drain pins and pin #s 16, 17, 29 voh1 ioh=-50ua 4 v output "h" voltage; pin #s16, 17, 29 voh2 ioh=-1ma 4 v output "l" voltage vol iol=8ma 0.45 v active 18 24 ma idle 1.3 4.0 ma power supply current idd power-down 50 80 ua rst pull-down resistor rrst vdd=5v 50 150 kohm pin capacitance cio 15 pf
myson technology MTV012A mtv012 a revision 1.1 12/23/1998 14 / 14 5 .4 ac characteristics at: ta=0 to 70 o c, vdd=4.0v ~ 6.0v, vss=0v name symbol condition min. typ. max. unit crystal frequency fxtal 8 mhz pwm dac frequency fda fxtal=8mhz 31.25 31.62 khz pwm dac frequency fda fxtal=12mhz 46.875 47.43 khz hs input pulse width thipw fxtal=8mhz 0.3 12 us vs input pulse width tvipw fxtal=8mhz 3 us hs input pulse width thipw fxtal=12mhz 0.2 8 us vs input pulse width tvipw fxtal=12mhz 2 us hsync to hblank output jitter thhbj 5 ns h+v to vblank output delay tvvbd fxtal=8mhz 16 us h+v to vblank output delay tvvbd fxtal=12mhz 10 us vs pulse width in h+v signal tvcpw fxtal=8mhz 32 us vs pulse width in h+v signal tvcpw fxtal=12mhz 20 us 6 .0 package dimension 40 pin pdip 600 mil mtv 012 52.197mm +/-0.127 15.494mm +/-0.254 2.540mm 0.457mm +/-0.127 1.270mm +/-0.254 1.981mm +/-0.254 3.81mm +/-0.127 1.778mm +/-0.127 0.254mm (min.) 3.302mm +/-0.254 13.868mm +/-0.102 16.256mm +/-0.508 0.254mm +/-0.102 5 o ~7 0 6 o +/-3 o

▲Up To Search▲

Price & Availability of MTV012A

	To Download MTV012A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .